Forward converters with active-clamp reset offer multiple benefits to designers and are presently finding wide use. Power converters based on the forward topology are particularly useful in applications where high efficiency and good power handling capability are required, mostly in the 50 W to 500 W output power range. While the popularity of the forward topology is based upon many factors, designers have primarily been drawn to its simplicity, performance, and efficiency. The forward converter is derived from the buck topology, however the transformer employed in the forward topology provides input-output ground isolation as well as a step-down or step-up function. The transformer in a forward topology does not inherently reset each switching cycle as do symmetrical topologies. A number of different reset mechanisms have been employed in forward power converters, each method having its own benefits and challenges.
FIGS. 1A-C illustrate the main operational steps of an active clamp forward power converter 100. FIG. 1A shows the active clamp forward power converter 100 at a time t0. At time t0, the main power switch Q1 110 is ON, applying the input voltage VIN across the primary winding 102 of the transformer 105. The resulting voltage at the secondary winding 103 of the transformer 105 is calculated as VIN (NS/NP), where NP and NS are the number of turns in the primary winding 102 and secondary winding 103, respectively. The primary current has two components at this time: the reflected current from the output inductor L1 130 represented as IL (NS/NP) and the current ramping up in the magnetizing inductance Lm 104. The reset switch Q2 140 is OPEN and the clamp capacitor CC 150 has been previously charged to a voltage of VIN/(1−D) in volts. This interval is the power phase, during which energy is transferred from the primary winding 102 to the secondary winding 103. The approximate duration of the power phase is TS (NP/NS)(VOUT/VIN), where TS is the switching period.
FIG. 1B shows the power converter 100 at a time t1, later than t0. At time t1, the main power switch Q1 110 is turned OFF and the reset switch Q2 140 is turned ON. The time t1 is generally known as the reset phase, because turning ON the reset switch Q2 140 resets the flux within the primary winding 102. The magnetizing current flows through the clamp capacitor CC 150 and the reset switch Q2 140 instead of through the main power switch Q1 110. Since the clamp capacitor CC 150 voltage is greater than VIN, the voltage across the primary winding 102 is now reversed with respect to the power phase t0. Because the potential across the magnetizing inductance Lm 104 has been reversed, the magnitude of the magnetizing current will decrease as the energy stored in the magnetizing inductance Lm 104 is transferred into the clamp capacitor CC 150. The voltage across the clamp capacitor CC 150 increases slightly during this period and peaks when the magnetizing current reaches zero.
FIG. 1C shows the power converter 100 at time t2, later than t1. At time t2, the current in the magnetizing inductance Lm 104 reaches zero and starts to build in the opposite direction. The current is sourced from the clamp capacitor CC 150 through the reset switch Q2 140 and travels through the magnetizing inductance Lm 104 and then back to the source (VIN). The current will continue to build in the opposite direction as the clamp capacitor CC 150 returns the energy that it had previously captured from the magnetizing inductance Lm 104. This is known as “reverse current” since current is being sourced back into VIN. Excessive reverse current may cause saturation of the transformer 105, leading to catastrophic failure of the power converter 100 and therefore should be contained to a manageable level. Steady state conditions require the clamp capacitor CC 150 voltage to return to the starting potential and the magnetizing current at the conclusion of the reset time to reach the same magnitude and opposite polarity as the current at the beginning of this reset time. At the conclusion of t2, the switching period is over, as defined by the controller oscillator period being over. The flux within the transformer 105 will naturally be balanced, as represented by the equation VON (D*TS)=VOFF (1−D)TS, where D is the duty cycle of the clock signal controlling the main power switch Q1 110. VOFF is the voltage that becomes applied across the primary winding 102 when there is no drive signal applied to Q1 110.
The voltage the clamp capacitor CC 150 measured at the bottom of the primary winding 102 drops below 0 during the OFF time of the duty cycle, calculated as (1−D)TS, as a result of the voltage stored in the clamp capacitor CC 150. The voltage is positive at the node A of FIG. 1C during the time at which Q1 110 is OFF and Q2 140 is ON. The voltage is represented as VDS=VIN/(1−D). Because VIN=(NP/NS)(1/D)VOUT, or VIN=K/D where K is a defined constant (NP/NS)VOUT, then VDS=VIN/(1−(K/VIN)).
As can be seen, VDS is a function of either VIN and D, or VIN and K. D should not approach one, or VDS will increase to a point where Q1 110 may be destroyed. Therefore, the voltage across CC 150 during time t2 is also impressed across the drain-source of Q1 110. As a result, an appropriate transistor must be selected to handle this voltage. However, as is known, a transistor having a larger VDS rating, meaning it can handle higher potentials across its drain-source, is physically bigger, more expensive, and less efficient. It is desirable to keep that voltage at the time t2 as low as possible so as to be able to make Q1 110 as small as possible, thereby making Q1 less expensive, more efficient and, in terms of form factor, more desirable.
FIG. 2 shows graphs 200 of driving signals 210, 220, 230 used to operate an active clamp forward converter such as the converter 100 of FIGS. 1A-C. The driving signal 210 is the signal applied to the main power switch Q1 110 and reset or auxiliary switch Q2 140 of the power converter 100 of FIGS. 1A-C. The ON time DTS is when Q1 110 is driven ON and Q2 140 is driven OFF. The opposite is true for the time (1−D)TS. The ratio between the time DTS and TS is known as the duty cycle, D, and TS is the commonly known switching time where 1/TS is the switching frequency. VLM 220, the voltage across Lm 104, oscillates between VON, during the ON time DTS, and VOFF, during the OFF time (1−D)TS. There is a short dead time from the time Q1 110 turns OFF until Q2 140 turns ON and vice versa. This dead time affects the duty cycle D only slightly. For simplicity, this dead time is not shown in FIG. 2 and is not accounted for in this disclosure. Finally, ILM 230, the magnetizing current, represents the current through the magnetizing inductance Lm 104 during the various stages of the switching cycle TS. It is referenced as positive when flowing from the voltage source such as VIN to Lm and negative when flowing into VIN from Lm.
FIG. 3A illustrates how the transformer 100 suffers flux imbalance during a low-to-high transient. FIG. 3A shows a graph 240 of a duty cycle D of the transformer 100 versus time, a graph 250 of a corresponding transformer magnetizing voltage versus time, and a graph 260 of a corresponding transformer magnetizing current versus time, with the horizontal axes of all the graphs 240, 250, and 260 aligned. As shown in FIG. 3A, as the duty cycle D increases rapidly in response to a transient condition, such as a low-to-high load transient, the duration of the positive segment of the transformer magnetizing voltage increases, and the transformer magnetizing current steadily increases. This results in a positive flux imbalance in the magnetizing inductance Lm 104.
FIG. 3B illustrates how the transformer 100 suffers flux imbalance during a high-to-low transient. FIG. 3B shows a graph 270 of a duty cycle D of the transformer 100 versus time, a graph 280 of a corresponding transformer magnetizing voltage versus time, and a graph 290 of a corresponding transformer magnetizing current versus time, with the horizontal axes of all the graphs 270, 280, and 290 aligned. As shown in FIG. 3B, as the duty cycle D decreases rapidly in response to a transient condition, such as a high-to-low load transient, the duration of the positive segment of the transformer magnetizing voltage decreases, and the transformer magnetizing current steadily decreases. This results in a negative flux imbalance in the magnetizing inductance Lm 104.
As shown in FIGS. 3A and 3B, both steadily increasing and steadily decreasing transformer magnetizing currents lead to saturation of the magnetizing inductance Lm 104 and, ultimately, catastrophic failure of the transformer 105 and/or other components connected to it.